ARTICLE INFO

ABSTRACT

Received date: 07/08/2015

Accepted date: 26/11/2015

In recent years, rapid development of multimedia applications leads to the requirement of huge data storage and high-speed data transfer capacity so that data compression emerges as an attractive topic. However, it is hard to compress sudden-changing signals, especially in high-speed and real-time processing. This paper proposes a hardware solution for real-time signal compression based on Daubechies wavelet transform (Db WT). The set of Db WT factors has been modified into integer number in order to be suitable for hardware implementation. The experiments were conducted on FPGA prototype implementation of real-time speech compression for evaluating the proposed approach.

KEYWORDS

Altera DE2, DWT, FPGA, speech compression, Verilog HDL

Cited as: Tuyen, T.P., 2015. FPGA implementation of lifting scheme daubechies discrete wavelet transform for real-time signal compression. Can Tho University Journal of Science. 1: 19-26.