Conventionally, to investigate the aging effects in analog-circuit-design phase, it requires to simulate, modify and verify iteratively on a number of circuit samples. In this work, we propose a fast aging simulation scheme for analog circuit modification and verification process based on the delta model in which the delta circuits are made from the delta devices built with the aging effect models by Verilog-A. During simulation, the aging device parameters are also updated continuously to attain the same accuracy with works in the literature; however, we only simulate the signal-difference between two similar circuits by re-using the previous simulation results to accelerate the aging simulation process. The experiment results show that, in the scenario of channel hot carrier effect on an analog amplifier circuit, the aging simulation process of the proposed scheme can be sped-up 10 times compared to that of conventional scheme with almost the same accuracy.